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VISION Computing Architecture

CV181x

RISC-V Vision SoC for Lightweight Intelligent Scenarios

Product Brief

The CV181 series is a high-performance visual processor tailored for the lightweight intelligent (consumer-grade) market. It leverages a Dual RISC-V C906 architecture (1.0GHz + 0.7GHz) or an ARM A53 + RISC-V combination in the 'A' series, providing an optimal balance of compute power and energy efficiency.

Featuring an integrated TPU delivering 0.5 to 1.0 TOPS @ INT8, the CV181 supports advanced AI tasks with BF16 mixed precision. It is optimized for fast boot scenarios and low power operation, making it ideal for battery-powered devices like smart doorbells and cat-eye locks.

The imaging pipeline is powered by a self-developed ISP supporting 3D noise reduction, two-frame wide dynamic range (2f-HDR), and lens distortion correction (LDC). It can handle up to two MIPI/DVP camera inputs and provide output via MIPI DSI, LVDS, or RGB interfaces.

Video processing capabilities include hardware H.265/H.264/MJPEG encoding at resolutions up to 5MP (2880x1620) @ 30FPS. The chip also integrates a 16-bit audio codec and a dedicated MCU subsystem for low-level control and peripheral management.

The CV181 series is designed for seamless integration, offering Pin-to-Pin compatibility within its package types (BGA 10x10 or QFN-88 9x9) and sharing a common SDK and TPU development environment with the CV180 series.

Dual Core Compute

Flexible architecture with pure RISC-V or ARM+RISC-V options to suit different performance and OS requirements.

2f-HDR Imaging

Advanced two-frame wide dynamic range technology ensures clear visibility in challenging backlit or high-contrast environments.

Integrated SiP Memory

Available with 512Mb DDR2 to 4Gbit DDR3 integrated SiP, reducing PCB footprint and BOM complexity.

Multi-Sensor Input

Supports up to 2 camera inputs with flexible interfaces including MIPI CSI, Sub-LVDS, and HiSPi.

Rich Audio/Visual I/O

Integrated 16-bit audio codec and comprehensive display outputs for interactive smart devices.

Eco-System Synergy

Shares SDK, ISP settings, and AI reference designs with the CV180 series for low-cost portfolio development.

System Architecture

CV181x Architecture Diagram Coming Soon
Key Innovation 01
Dual Cores: C906 (1.0GHz+0.7GHz) or ARM A53 (1.2GHz)+C906
Key Innovation 02
TPU: 0.5 ~ 1.0 TOPS @ INT8 / BF16 Supported
Key Innovation 03
ISP: 3DNR, 2f-HDR, LDC, 3A, Dehaze
Key Innovation 04
Video: 5MP@30fps H.265/H.264/MJPEG
Key Innovation 05
Display: MIPI DSI (4L/2L), LVDS, RGB, BT.656/1120
Key Innovation 06
Fast Boot & Low Power Architecture
High Performance Compute

AI Performance

The integrated TPU provides specialized acceleration for lightweight neural networks, optimized for common consumer AI tasks.

Optimized for person detection and gesture recognition.
Supports Caffe, TensorFlow, Pytorch, and ONNX frameworks.
High efficiency inference for real-time edge responses.

Benchmarks & Metrics

Peak Compute1.0 TOPS @ INT8
Mixed PrecisionBF16 / INT8
SDKShared TPU Toolchain
Advanced ISP Pipeline

Imaging Pipeline

Self-developed ISP engine focused on clarity and dynamic range for high-definition consumer vision.

MODULE-01

3DNR

Advanced noise reduction for low-light scenes.

MODULE-02

2f-HDR

Superior contrast handling in complex lighting.

MODULE-03

LDC

Lens distortion correction for wide-angle sensors.

MODULE-04

Display Engine

Multi-interface output support (MIPI/LVDS/RGB).

Variant Comparison

ModelCPUTPUDDR SiPPackage
CV1813HDual C9061.0 TOPS4Gbit DDR3BGA 10x10
CV1812HDual C9061.0 TOPS2Gbit DDR3BGA 10x10
CV1811HDual C9061.0 TOPS1Gbit DDR3BGA 10x10
CV1812C-PDual C9061.0 TOPS2Gbit DDR3QFN-88 9x9
CV1811CDual C9060.5 TOPS1Gbit DDR3QFN-88 9x9
CV1810CDual C9060.5 TOPS512Mb DDR2QFN-88 9x9
CV1813H-AA53+C9061.0 TOPS4Gbit DDR3BGA 10x10
CV1812H-AA53+C9061.0 TOPS2Gbit DDR3BGA 10x10
CV1811H-AA53+C9061.0 TOPS1Gbit DDR3BGA 10x10
CV1812C-PAA53+C9061.0 TOPS2Gbit DDR3QFN-88 9x9
CV1811C-AA53+C9061.0 TOPS1Gbit DDR3QFN-88 9x9

Commercial Deployment Scenarios

Home IPC

Home IPC

Smart Doorbell

Smart Doorbell

Cat-eye Door Lock

Cat-eye Door Lock

Streaming Rearview Mirror

Streaming Rearview Mirror

Access Control

Access Control

Dash Cam

Dash Cam

Datasheet

Technical Reference
Processor
CPUDual C906 1.0GHz + 0.7GHz (or ARM A53+C906)
AI
TPU0.5 ~ 1.0 TOPS @ INT8 / BF16
Video
EncodingH.265/H.264/MJPEG (Max 5MP@30)
ISP3DNR, 2f-HDR, LDC, Dehaze
Interface
Video In2x (MIPI 2L+2L+DVP or 4L)
Video OutMIPI DSI (4L/2L), LVDS, RGB, BT.656/1120
Memory
SiP DDR512Mb DDR2 / 1Gbit / 2Gbit / 4Gbit DDR3
Storage
InterfaceeMMC, SPI NOR/NAND, SDIO 3.0 x2
Ethernet
MAC/PHY10/100 MAC PHY (RMII Supported)
Peripherals
I/OUSB 2.0, I2C x5, SPI x3, UART x4, PWM x15
Audio
Codec16-bit Codec (ADC/DAC/I2S)
System
BootFast Boot / Secure Boot
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